Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Electronic systems designed to provide these benefits often include integrated circuits (ICs) that involve complicated timing issues. Appropriate timing design considerations are usually critical for a device to achieve proper functionality. Establishing appropriate timing design values is often very complex and consumes significant resources.
The complexity of commonly used integrated circuits has advanced dramatically and design efforts usually require the assistance of computer aided design (CAD) tools. The automated development of complex integrated circuits such as application specific integrated circuits (ASICs) is referred to as electronic design automation (EDA). EDA tools are usually software programs that provide instructions to a computer for processing information associated with a circuit design. Usually, input information for an EDA tool includes characteristics and functional attributes of a circuit in varying levels of abstraction (e.g., from functional operation to physical structure). It is often convenient to group various components of complex circuits (e.g., an ASC) into a “block” or “cell” that performs a particular function or operation. The cells are combined to obtain a desired integrated circuit device design. These cells are often described and included in an EDA tool cell file. For example a cell file can represent a sequential element (e.g., a flip flop, a latch, etc.), a combinational logic element (e.g., an AND gate, OR gate, etc.) and/or both a circuit that includes both types of elements.
Cells files that include sequential elements are usually assigned timing values including delay, setup, and hold values. The actual delay, setup and hold values are determined by the inherent characteristics of the components included in each cell. The sequential cell delay, setup, and hold characteristics of a cell directly affect the proper functionality of a circuit. The characteristics are utilized in determining a variety of design constraints and making a number of design decisions. For example, delay, setup and hold timing constrains directly impact the maximum possible frequency at which an integrated circuit can reliable operate to provide desired functionality. Since delay, setup and hold characteristics are often crucial to the proper functionality of a device, including appropriate values in an EDA cell file is very important.
Traditional attempts at ascertaining appropriate delay, setup and hold values usually rely upon assumptions that may not be accurate and often result in design errors. For example, some traditional methods acquire the delay as a function of input-slope and output load and acquire setup and hold as a function of input slope on the clock and data signals. Attempts at delay characterization for each input slope and output load often rely on an assumption that a data signal transition occurs well before a clock transition and is held long after the clock transition. Previous attempts at setup and hold characterization for each clock and data input are often also based upon conditions that may not reflect reality and often usually miss characterize actual values.
Traditional attempts include various permutation that take a limited approach to the interdependence of delay, setup and hold characteristics which can result in failures when implemented in silicon. For example, acquiring a setup time with infinite hold time and then acquiring a hold time with infinite setup time, for functional failure, usually does not provide values that accurately reflect actual setup and hold time. In addition, acquiring a setup time with infinite hold time and then acquiring a hold time based on the acquired setup time, for functional failure, also usually falls short of an accurate reflection of appropriate setup and hold times for a silicon circuit. Alternatively, some traditional attempts try to acquire values in a similar manner except the setup and hold acquisition is performed for a percentage delay degradation of the acquired delay instead of functional failure. The attempts relying on a percentage of delay degradation can lead to significant design flaws in some applications.
What is required is a method that facilitates consideration of the interdependence of the delay, setup and hold values.